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LTC2383-16 16-Bit, 1Msps, Low Power SAR ADC with Serial Interface FEATURES
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DESCRIPTION
The LTC(R)2383-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2383-16 has a 2.5V fully differential input range. The LTC2383-16 consumes only 13mW and achieves 2LSB INL max, no missing codes at 16-bits and 92dB SNR. The LTC2383-16 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisychain mode. The fast 1Msps throughput with no cycle latency makes the LTC2383-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2383-16 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate.
LTC238X-16 SAR ADC Family
PART NUMBER LTC2383-16 LTC2382-16 LTC2381-16 RESOLUTION 16 16 16 SPEED 1Msps 500ksps 250ksps POWER 13mW 6.5mW 3.25mW
1Msps Throughput Rate 2LSB INL (Max) Guaranteed 16-Bit No Missing Codes Low Power: 13mW at 1Msps, 13W at 1ksps 92dB SNR (typ) at fIN = 20kHz Guaranteed Operation to 125C 2.5V Supply Fully Differential Input Range 2.5V External 2.5V Reference Input No Pipeline Delay, No Cycle Latency 1.8V to 5V I/O Voltages SPI-Compatible Serial I/O with Daisy-Chain Mode Internal Conversion Clock 16-pin MSOP and 4mm x 3mm DFN Packages
APPLICATIONS
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Medical Imaging High Speed Data Acquisition Portable or Compact Instrumentation Industrial Process Control Low Power Battery-Operated Instrumentation ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
32k Point FFT fS = 1Msps, fIN = 20kHz
2.5V 10F 1.8V TO 5V 0.1F AMPLITUDE (dBFS) 0 -20 ANALOG INPUT 0V TO 2.5V 50 LT6350 50 SINGLE-ENDEDTO-DIFFERENTIAL DRIVER 100 3300pF IN- 100 REF 2.5V 47F (X5R, 0805 SIZE) GND IN+ -40 -60 -80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY (kHz) 400 500 SNR = 92.2dB THD = -106.2dB SINAD = 92dB SFDR = 110.4dB
VDD LTC2383-16
OVDD
CHAIN RDL/SDI SDO SCK BUSY CNV
23816 TA01
SAMPLE CLOCK
238316 TA02
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LTC2383-16 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD) ...............................................2.8V Supply Voltage (OVDD) ................................................6V Reference Input (REF)..............................................2.8V Analog Input Voltage (Note 3) IN+, IN- ......................... (GND -0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3)........................... (GND -0.3V) to (OVDD + 0.3V)
Digital Output Voltage (Note 3)........................... (GND -0.3V) to (OVDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC2383C ................................................ 0C to 70C LTC2383I .............................................-40C to 85C LTC2383H .......................................... -40C to 125C Storage Temperature Range .................. -65C to 150C
PIN CONFIGURATION
TOP VIEW CHAIN VDD GND IN
+
1 2 3 4 5 6 7 8 17 GND
16 GND 15 OVDD 14 SDO 13 SCK 12 RDL/SDI 11 BUSY 10 GND 9 CNV
TOP VIEW CHAIN VDD GND IN+ IN- GND REF REF 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OVDD SDO SCK RDL/SDI BUSY GND CNV
IN- GND REF REF
DE PACKAGE 16-LEAD (4mm 3mm) PLASTIC DFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
MS PACKAGE 16-LEAD (4mm 5mm) PLASTIC MSOP TJMAX = 150C, JA = 110C/W
ORDER INFORMATION
LEAD FREE FINISH LTC2383CMS-16#PBF LTC2383IMS-16#PBF LTC2383HMS-16#PBF LTC2383CDE-16#PBF LTC2383IDE-16#PBF TAPE AND REEL LTC2383CMS-16#TRPBF LTC2383IMS-16#TRPBF LTC2383HMS-16#TRPBF LTC2383CDE-16#TRPBF LTC2383IDE-16#TRPBF PART MARKING 238316 238316 238316 23836 23836 PACKAGE DESCRIPTION 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2383-16 ELECTRICAL CHARACTERISTICS
SYMBOL VIN+ VIN - VIN+ - VIN- VCM IIN CIN CMRR PARAMETER Absolute Input Range (IN+) Absolute Input Range (IN-) Input Differential Voltage range Common-Mode Input Range Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio Sample Mode Hold Mode
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 5) (Note 5) VIN = VIN+ - VIN-
l l l l l
MIN -0.05 -0.05 -VREF VREF/2- 0.05
TYP
MAX VREF VREF +VREF
UNITS V V V V A pF pF dB
VREF/2
VREF/2+ 0.05 1
45 5 70
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL PARAMETER Resolution No Missing Codes Transition Noise INL DNL BZE FSE Integral Linearity Error Differential Linearity Error Bipolar Zero-Scale Error Bipolar Zero-Scale Error Drift Bipolar Full-Scale Error Bipolar Full-Scale Error Drift (Note 7)
l
CONVERTER CHARACTERISTICS
CONDITIONS
l l l l l
MIN 16 16
TYP
MAX
UNITS Bits Bits
0.6 (Note 6) (Note 7) -2 -1 -6 -14 0.8 0.4 0.25 3 3 0.1 14 2 1 6
LSBRMS LSB LSB LSB mLSB/C LSB ppm/C
DYNAMIC ACCURACY
SYMBOL PARAMETER SINAD SNR THD SFDR
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS. (Notes 4, 8)
CONDITIONS fIN = 20kHz fIN = 20kHz fIN = 20kHz, First 5 Harmonics fIN = 20kHz
l l l
MIN 88.5 89
TYP 92 92 -106 108 30 2 30
MAX
UNITS dB dB
Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range -3dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response
-99
dB dB MHz ns ps ns
Full-Scale Step
250
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LTC2383-16 REFERENCE INPUT
SYMBOL VREF IREF PARAMETER Reference Voltage Load Current
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 5) (Note 9)
l l
MIN 2.4
TYP
MAX 2.6 910
UNITS V A
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current Output Source Current Output Sink Current IO = -500 A IO = 500 A VOUT = 0V to OVDD VOUT = 0V VOUT = OVDD VIN = 0V to OVDD CONDITIONS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN
l l l l l l
TYP
MAX 0.2 * OVDD
UNITS V V A pF V
0.8 * OVDD -10 5 OVDD - 0.2 0.2 -10 -10 10 10 10
V A mA mA
POWER REQUIREMENTS
SYMBOL VDD OVDD IDD PARAMETER Supply Voltage Supply Voltage Supply Current Power Down Mode Power Down Mode Power Dissipation Power Down Mode Power Down Mode
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l l l
MIN 2.375 1.71
TYP 2.5 5.2 0.5 0.5 13 1.25 1.25
MAX 2.625 5.25 6.5 40 110 16.25 100 275
UNITS V V mA A A mW W W
1Msps Sample Rate Conversion Done Conversion Done (H-Grade) 1Msps Sample Rate Conversion Done Conversion Done (H-Grade)
PD
ADC TIMING CHARACTERISTICS
SYMBOL fSMPL tCONV tACQ tCYC tCNVH tBUSYLH tCNVL tSCK tSCKH PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Time Between Conversions CNV High Time CNV to BUSY Delay Minimum Low Time for CNV SCK Period SCK High Time
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l
MIN 610 250 1 20
TYP
MAX 1 730
UNITS Msps ns ns us ns
tACQ = tCYC -tCONV - tBUSYLH (Note 10)
l l l l l l l
CL = 20pF (Note 11) (Note 11) (Notes 11, 12)
20 200 10 4
ns ns ns ns
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LTC2383-16 ADC TIMING CHARACTERISTICS
SYMBOL tSCKL tSSDISCK tHSDISCK tSCKCH tDSDO tHSDO tDSDOBUSYL tEN tDIS tSSCKRDL tHSCKRDL PARAMETER SCK Low Time SDI Setup Time From SCK SDI Hold Time From SCK SCK Period in Chain Mode SDO Data Valid Delay from SCK SDO Data Remains Valid Delay from SCK SDO Data Valid Delay from BUSY Bus Enable Time After RDL Bus Relinquish Time After RDL SCK Setup Time from RDL/SDI SCK Hold Time from RDL/SDI (Note 11) (Note 11) tSCKCH = tSSDISCK + tDSDO (Note 11) CL = 20pF (Note 11) CL = 20pF (Note 10) CL = 20pF (Note 10) (Note 11) (Note 11) (Note 10) (Note 10)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l l l l l l l l l l
MIN 4 4 1 13.5
TYP
MAX
UNITS ns ns ns ns
9.5 1 5 16 13 1 16
ns ns ns ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may effect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above REF or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without latch-up. Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 1MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from -0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of -FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale 2.5V input with a 2.5V reference voltage. Note 9: fSMPL = 1MHz, IREF varies proportionately with sample rate. Note 10: Guaranteed by design, not subject to test. Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 12: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture.
0.8*OVDD 0.2*OVDD tDELAY 0.8*OVDD 0.2*OVDD tDELAY 0.8*OVDD 0.2*OVDD 50%
tWIDTH 50%
238316F01
Figure 1. Voltage Levels for Timing Specifications
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LTC2383-16
fSMPL = 1Msps, unless otherwise noted. Integral Nonlinearity vs Output Code
2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 16384 32768 49152 OUTPUT CODE 65536
238316 G01
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity vs Output Code
1.0
TA = 25C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
DC Histogram
1600000 1400000
0.5 COUNTS
1200000 1000000
0.0
800000 600000 400000
-0.5 200000 -1.0 0 16384 32768 49152 OUTPUT CODE 65536
238316 G02
0 32766
32767
32768 CODE
32769
32770
238316 G03
32k Point FFT fS = 1Msps, fIN = 20kHz
0 -20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY (kHz) 400 500
238316 G04
SNR, SINAD vs Input Frequency
93 92 91 SNR, SINAD (dBFS) 90 89 88 87 86 85 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz)
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THD, Harmonics vs Input Frequency
-80 -85 HARMONICS, THD (dBFS)
SNR = 92.2dB THD = -106.2dB SINAD = 92dB SFDR = 110.4dB
SNR SINAD
-90 -95 -100 -105 -110 -115 -120 -125 -130 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz)
238316 G06
THD
2ND
3RD
SNR, SINAD vs Input level, fIN = 20kHz
93.0 94.00 93.50
SNR, SINAD vs Temperature
-100.00
THD, Harmonics vs Temperature
92.5 SNR, SINAD (dBFS) SNR, SINAD (dBFS) SINAD 93.00 92.50 92.00 91.50 91.0 -40 91.00 -55 -35 -15 SNR SINAD
HARMONICS, THD (dBFS)
SNR
-105.00
THD
2ND -110.00 3RD -115.00
92.0
91.5
-30
-20 -10 INPUT LEVEL (dB)
238316 G07
0
5 25 45 65 85 105 125 TEMPERATURE (C)
238316 G08
-120.00 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
3653 G03
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LTC2383-16 TYPICAL PERFORMANCE CHARACTERISTICS
fSMPL = 1Msps, unless otherwise noted. INL/DNL vs Temperature
1 MAX INL FULL-SCALE ERROR (LSB) INL/DNL ERROR (LSB) 0.5 MAX DNL 0 MIN DNL -0.5 MIN INL -1 -55 -35 -15 2.5
TA = 25C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
Full-Scale Error vs Temperature
0.3
Offset Error vs Temperature
2.0 OFFSET ERROR (LSB) -FS 1.5 +FS 1.0
0.2
0.1
0
0.5
5 25 45 65 85 105 125 TEMPERATURE (C)
238316 G10
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
238316 G11
-0.1 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
238316 G12
Supply Current vs Temperature
6 POWER SUPPLY CURRENT (mA) 5 4 3 2 1 0 -55 -35 -15 IREF IOVDD 5 25 45 65 85 105 125 TEMPERATURE (C)
238316 G13
Shutdown Current vs Temperature
30 IVDD + IOVDD + IREF POWER SUPPLY CURRENT (mA) 6 5 4 3 2 1 0 5 25 45 65 85 105 125 TEMPERATURE (C)
238316 G14
Supply Current vs Sampling Rate
IVDD POWER-DOWN CURRENT (A)
25 20 15 10 5 0 -55 -35 -15
0
200
400 600 800 SAMPLING RATE (kHz)
1000
238316 G15
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LTC2383-16 PIN FUNCTIONS
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2383-16 operates in Normal Mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2383-16 operates in Chain Mode and the RDL/SDI pin functions as SDI, the daisychain serial data input. VDD (Pin 2): 2.5V Digital Power Supply. The range of VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10F ceramic capacitor. GND (Pins 3, 6, 10 and 16): Ground. IN+, IN- (Pins 4, 5): Positive and Negative Differential Analog Inputs. REF (Pins 7, 8): Reference Input. The range of REF is 2.4V to 2.6V. This pin is referred to the GND pin and should be decoupled closely to the pin with a 47F ceramic capacitor (X5R, 0805 size). CNV (Pin 9): Convert Input. A rising edge on this input initiates a new conversion. When the conversion is done, the part powers down as long as CNV is held high. When CNV is returned low, the part powers up in preparation for the next conversion. BUSY (Pin 11): BUSY indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. RDL/SDI (Pin 12): When CHAIN is low, the part is in Normal Mode and the pin is treated as a bus enabling input. When CHAIN is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another ADC in the daisychain is input. SCK (Pin 13): Serial Data Clock Input. When SDO is enabled, the conversion result or daisychain data from another ADC is shifted out on the rising edges of this clock MSB first. SDO (Pin 14): Serial Data Output. The conversion result or daisychain data is output on this pin on each rising edge of SCK MSB first. The output data is in 2's complement format. OVDD (Pin 15): I/O Interface Digital Power. The range of OVDD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V, or 5V). Bypass OVDD to GND with a 0.1F capacitor. GND (Exposed Pad Pin 17 - DFN Package Only): Ground. Exposed pad must be soldered directly to the ground plane.
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V REF = 2.5V LTC2383-16 CHAIN SDO RDL/SDI SCK OVDD = 1.8V to 5V
IN+
+
16-BIT SAMPLING ADC IN-
-
SPI PORT
CONTROL LOGIC GND
238316 BD01
CNV BUSY
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LTC2383-16 TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0 POWER-UP CNV POWER-DOWN
ACQUIRE BUSY CONVERT
SCK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
238316 TD02
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LTC2383-16 APPLICATIONS INFORMATION
The LTC2383-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a single 2.5V supply, the LTC2383-16 supports a large 2.5V fully differential input range, making it ideal for high performance applications which require a wide dynamic range. The LTC2383-16 achieves 2LSB INL max, no missing codes at 16-bits and 92dB SNR. Fast 1Msps throughput with no cycle latency makes the LTC2383-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2383-16 dissipates only 13mW at 1Msps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. CONVERTER OPERATION The LTC2383-16 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A converter (CDAC) is connected to the IN+ and IN- pins to sample the differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the 16-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 ... VREF/65536) using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 16-bit digital output code for serial transfer. TRANSFER FUNCTION The LTC2383-16 digitizes the full-scale voltage of 2 x REF into 216 levels, resulting in an LSB size of 76V with REF = 2.5V. The ideal transfer function is shown in Figure 2. The output data is in 2's complement format. ANALOG INPUT The analog inputs of the LTC2383-16 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent
238316 F03
OUTPUT CODE (TWO'S COMPLEMENT)
OVERVIEW
011...111 011...110 BIPOLAR ZERO
000...001 000...000 111...111 111...110
100...001 100...000 -FSR/2
FSR = +FS - -FS 1LSB = FSR/65536 -1 0V 1 FSR/2 - 1LSB LSB LSB INPUT VOLTAGE (V)
238316 F02
Figure 2. LTC2383-16 Transfer Function
circuit shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each input sees approximately 45pF (CIN) from the sampling CDAC in series with 40 (RON) from the on-resistance of the sampling switch. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the ADC. The inputs draw a current spike while charging the CIN capacitors during acquisition. During conversion, the analog inputs draw only a small leakage current.
REF RON IN+ CIN
REF IN- RON CIN
BIAS VOLTAGE
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2383-16
INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance inputs of the LTC2383-16 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling
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LTC2383-16 APPLICATIONS INFORMATION
time is important even for DC inputs, because the ADC inputs draw a current spike when entering acquisition. For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2383-16. The amplifier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the current spike the ADC inputs draw. Input Filtering The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise. The simple 1-pole RC lowpass filter (LPF1) shown in Figure 4 is sufficient for many applications. Another filter network consisting of LPF2 and the 100 series input resistors should be used between the buffer and ADC inputs to both minimize the noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients. Long RC time constants at the analog inputs will slow down the settling of the analog inputs. Therefore, LPF2 requires a wider bandwidth than LPF1. A buffer amplifier with a low noise density must be selected to minimize degradation of the SNR. With the 482kHz lowpass filter shown in Figure 4, the LT6350 provides the full data sheet performance of the LTC2383-16. High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.
SINGLE-ENDEDINPUT SIGNAL LPF1 500 6600pF 50 100 SINGLE-ENDED- BW = 482kHz BW = 48kHz TO-DIFFERENTIAL DRIVER LT6350 LPF2 50 3300pF IN-
238316 F04
Single-Ended-to-Differential Conversion For single-ended input signals, a single-ended to differential conversion circuit must be used to produce a differential signal at the inputs of the LTC2383-16. The LT6350 ADC driver is recommended for performing single-ended-todifferential conversions.The LT6350 is flexible and may be configured to convert single-ended signals of various amplitudes to the 2.5V differential input range of the LTC2383-16. The LT6350 is also available in H-grade to complement the extended temperature operation of the LTC2383-16 up to 125C. Figure 5 shows the LT6350 being used to convert a 0V to 2.5V single-ended input signal. In this case, the first amplifier is configured as a unity gain buffer and the singleended input signal directly drives the high-impedance input of the amplifier. As shown in the FFT of Figure 5a, the LT6350 drives the LTC2383-16 to full datasheet performance without degrading the SNR or THD .
LT6350 4 8 0V to 2.5V 1 OUT1 0V to 2.5V
+ -
RINT
RINT
2
- +
VCM = VREF/2
5
OUT2
2.5V to 0V
+ -
238316 F05
Figure 5. LT6350 Converting a 0V-2.5V Single-Ended Signal to a 2.5V Differential Input Signal
0 -20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY (kHz) 400 500
238316 F05a
SNR = 92.2dB THD = -106.2dB SINAD = 92dB SFDR = 110.4dB
100
IN+ LTC2383-16
Figure 4. Input Signal Chain
Figure 5a. 32k Point FFT Plot for Circuit Shown in Figure 5
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LTC2383-16 APPLICATIONS INFORMATION
The LT6350 can also be used to buffer and convert singleended signals larger than the input range of the LTC2383-16 in order to maximize the signal swing that can be digitized. Figure 6 shows the LT6350 converting a 0V-5V single-ended input signal to the 2.5V differential input range of the LTC2383-16. In this case, the first amplifier in the LT6350 is configured as an inverting amplifier stage, which acts to attenuate the input signal down to the 0V-2.5V input range of the LTC2383-16. In the inverting amplifier configuration, the single-ended input signal source no longer directly drives a high impedance input of the first amplifier. The input impedance is instead set by resistor RIN. RIN must be chosen carefully based on the source impedance of the signal source. Higher values of RIN tend to degrade both the noise and distortion of the LT6350 and LTC2383-16 as a system. R1, R2 and R3 must be selected in relation to RIN to achieve the desired attenuation and to maintain a balanced input impedance in the first amplifier. Table 1 shows the
VREF R2 = 1k 150pF
resulting SNR and THD for several values of RIN , R1, R2 and R3 in this configuration. Figure 6a shows the resulting FFT when using the LT6350 as shown in Figure 6. The LT6350 can also be used to buffer and convert large, true bipolar signals which swing below ground to the 2.5V differential input range of the LTC2383-16. Figure 7 shows the LT6350 being used to convert a 10V true bipolar signal for use by the LTC2383-16. The input impedance is again set by resistor RIN. Table 2 shows the resulting SNR and THD for several values of RIN. Figure 7a shows the resulting FFT when using the LT6350 as shown in Figure 7.
Table 1. SNR, THD vs RIN for 0-5V Single-Ended Input Signal.
RIN () 2k 10k 100k
VCM R2 = 1.24k 200pF
R1 () 1k 5k 50k
R2 () 1k 5k 50k
R3 () 2k 10k 100k
R4 () 665 3.3k 16k
SNR (dB) 92 91 91
THD (dB) -101 -100 -94
LT6350 4 OUT1 8
LT6350 4 OUT1 8
10F
R4 = 665 R3 = 2k 1 RIN = 2k
+ -
RINT
RINT
2.5V to 0V
10F R4 = 1.1k R3 = 10k
+ -
RINT
RINT
2.5V to 0V
2 R1 = 1k
- +
5
OUT2
0V to 2.5V RIN = 10k 10V
1 R1 = 1.24k
2
- +
VCM = VREF/2
5
OUT2
0V to 2.5V
+ VCM = VREF/2 -
238316 F06
+ -
0V to 5V
75pF
220pF
238316 F07
Figure 6. LT6350 Converting a 0V-5V Single-Ended Signal to a 2.5V Differential Input Signal
0 -20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY (kHz) 400 500
238316 F06a
Figure 7. LT6350 Converting a 10V Single-Ended Signal to a 2.5V Differential Input Signal
0 -20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY (kHz) 400 500
238316 F07a
SNR = 92dB THD = -101dB SINAD = 91.4dB SFDR = 103dB
SNR = 92dB THD = -97dB SINAD = 91.2dB SFDR = 99.7dB
Figure 6a. 32k Point FFT Plot for Circuit Shown in Figure 6
Figure 7a. 32k Point FFT Plot for Circuit Shown in Figure 7
238316f
12
LTC2383-16 APPLICATIONS INFORMATION
Table 2. SNR, THD vs RIN for 10V Single-Ended Input Signal.
RIN () 10k 50k 100k R1 () 1.24k 6.19k 12.4k R2 () 1.24k 6.19k 12.4k R3 () 10k 50k 100k R4 () 1.1k 5.49k 11k SNR (dB) 92 91 91 THD (dB) -96 -96 -96
ADC REFERENCE The LTC2383-16 requires an external reference to define its input range. A low noise, low temperature drift reference is critical to achieving the full datasheet performance of the ADC. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power and high accuracy, the LTC6652-2.5 is particularly well suited for use with the LTC2383-16. The LTC6652-2.5 offers 0.05% (max) initial accuracy and 5ppm/C (max) temperature coefficient for high precision applications. The LTC6652-2.5 is fully specified over the H-grade temperature range and complements the extended temperature operation of the LTC2383-16 up to 125C. We recommend bypassing the LTC6652-2.5 with a 47F ceramic capacitor (X5R, 0805 size) close to the REF pin. All performance curves shown in this datasheet were obtained using the LTC6652-2.5. The REF pin of the LTC2383-16 draws charge (QCONV) from the 47F bypass capacitor during each conversion cycle. The reference replenishes this charge with a DC current, IREF = QCONV/tCYC. The DC current draw of the REF pin, IREF, depends on the sampling rate and output code. If the LTC2383-16 is used to continuously sample a signal at a constant rate, the LTC6652-2.5 will keep the deviation of the reference voltage over the entire code span to less than 0.5LSBs.
When idling, the REF pin on the LTC2383-16 draws only a small leakage current (< 1A). In applications where a burst of samples is taken after idling for long periods as shown in Figure 8, IREF quickly goes from approximately 0A to a maximum of 910A at 1Msps. This step in DC current draw triggers a transient response in the reference that must be considered since any deviation in the reference output voltage will affect the accuracy of the output code. In applications where the transient response of the reference is important, the fast settling LTC6655-2.5 reference is recommended. Inserting a 1 resistor between the 47F bypass capacitor and reference output as shown in Figure 9 helps to improve the transient settling time and minimize the reference voltage deviation.
VOUT_S LTC6655-2.5 VOUT_F 1 47F LTC2383-16
238316 F09
Figure 9. LTC6655-2.5 Driving REF of LTC2381-16
DYNAMIC PERFORMANCE Fast Fourier Transform (FFT) techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. The LTC2383-16 provides guaranteed tested limits for both AC distortion and noise measurements.
CNV IDLE PERIOD IDLE PERIOD
238316 F08
Figure 8. CNV Waveform Showing Burst Sampling
238316f
13
LTC2383-16 APPLICATIONS INFORMATION
Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 10 shows that the LTC2383-16 achieves a typical SINAD of 92dB at a 1MHz sampling rate with a 20kHz input.
0 -20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 100 200 300 FREQUENCY (kHz) 400 500
238316 F10
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. POWER CONSIDERATIONS The LTC2383-16 provides two power supply pins: the 2.5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2383-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Power Supply Sequencing The LTC2383-16 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2383-16 has a power-on-reset (POR) circuit that will reset the LTC2383-16 at initial power-up or whenever the power supply voltage drops below 1V. Once the supply voltage reenters the nominal supply voltage range, the POR will reinitialize the ADC. No conversions should be initiated until 20s after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. TIMING AND CONTROL CNV Timing The LTC2383-16 conversion is controlled by CNV. A rising edge on CNV will start a conversion. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2383-16 begins acquiring the input signal.
SNR = 92.2dB THD = -106.2dB SINAD = 92dB SFDR = 110.4dB
Figure 10. 32k Point FFT of the LTC2383-16
Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 10 shows that the LTC2383-16 achieves a typical SNR of 92dB at a 1MHz sampling rate with a 20kHz input. Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: V 22 + V 32 + V 42 + ... + VN 2 V1
THD = 20 log
238316f
14
LTC2383-16 APPLICATIONS INFORMATION
Internal Conversion Clock The LTC2383-16 has an internal clock that is trimmed to achieve a maximum conversion time of 730ns. With a minimum acquisition time of 250ns, throughput performance of 1Msps is guaranteed without any external adjustments. Auto Power-Down The LTC2383-16 automatically powers down after a conversion has been completed as long as CNV remains high. During power down, the data from the last conversion can be clocked out. To minimize power dissipation during power down, disable SDO and turn off SCK. To power up the part, bring CNV low at least 200ns (tCONVL) before the initiation of the next conversion. The auto power-down feature will reduce the power dissipation of the LTC238316 as the sampling frequency is reduced. Since the time required to power up the part does not change at lower sample rates, the LTC2383-16 can remain powered-down for a larger fraction of the conversion cycle (tCYC), thereby reducing the average power dissipation which scales linearly with sampling rate as shown in Figure 11.
6 POWER SUPPLY CURRENT (mA) 5 4 3 2 1 0 0 200 400 600 800 SAMPLING RATE (kHz) 1000
238316 F11
DIGITAL INTERFACE The LTC2383-16 has a serial digital interface. The flexible OVDD supply allows the LTC2383-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 60MHz, a 1Msps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D15 remains valid till the first rising edge of SCK. The serial interface on the LTC2383-16 is simple and straightforward to use. The following sections describe the operation of the LTC2383-16. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy-chained.
Figure 11. Power Supply Current of the LTC2383-16 Versus Sampling Rate
238316f
15
LTC2383-16 TIMING DIAGRAM
Normal Mode, Single Device When CHAIN = 0, the LTC2383-16 operates in Normal mode. In Normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high-impedance. If RDL/SDI is low, SDO is driven. Figure 12 shows a single LTC2383-16 operated in Normal Mode with CHAIN and RDL/SDI tied to ground. With RDL/ SDI grounded, SDO is enabled and the MSB(D15) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2383-16.
CONVERT CNV CHAIN LTC2383-16 RDL/SDI SCK CLK SDO DATA IN BUSY IRQ DIGITAL HOST
238316 F12a
ACQUIRE
CONVERT POWER-DOWN
ACQUIRE POWER-UP
CONVERT
CHAIN = 0 tCNVH CNV
tCYC
tCNVL
tACQ = tCYC - tCONV - tBUSYLH BUSY tBUSYLH tCONV tSCK tACQ
tSCKH
2 3 14 15 16
SCK
1
tHSDO tDSDOBUSYL SDO (RDL/SDI = 0) D15 D14 tDSDO D13
tSCKL
D1
D0
238316 F12
Figure 12. Using a Single LTC2383-16 in Normal Mode
238316f
16
LTC2383-16 TIMING DIAGRAM
Normal Mode, Multiple Devices Figure 13 shows multiple LTC2383-16 devices operating in Normal Mode(CHAIN = 0) sharing CNV, SCK and SDO. By sharing CNV, SCK and SDO, the number of required signals to operate multiple ADCs in parallel is reduced. Since SDO is shared, the RDL/SDI input of each ADC must be used to allow only one LTC2383-16 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 13, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. To ensure the MSB is properly output and captured, SCK must be held low at least 1ns before and 16ns after bringing RDL/SDI low.
RDL2 RDL1 CONVERT CNV CHAIN LTC2383-16 B RDL/SDI SCK SDO RDL/SDI SCK DATA IN CLK
238316 F13
CHAIN
CNV LTC2383-16 A
BUSY SDO
IRQ DIGITAL HOST
ACQUIRE
CONVERT POWER-DOWN
ACQUIRE POWER-UP
CONVERT
CHAIN = 0 CNV tCONV BUSY tBUSYLH RDL/SDIA tCNVL
RDL/SDIB tSCK 1 tSSCKRDL tEN Hi-Z D15A D14A D13A 2 3 tHSDO tDSDO D1A tDIS D0A Hi-Z D15B D14B D13B D1B D0B Hi-Z
238316 F13
tHSCKRDL SCK
tSCKH 14 15 16 tSCKL 17 18 19 30 31 32
SDO
Figure 13. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
238316f
17
LTC2383-16 TIMING DIAGRAM
When CHAIN = OVDD, the LTC2383-16 operates in Chain Mode. In Chain Mode, SDO is always enabled and RDL/SDI serves as the serial data input pin (SDI) where daisychain data output from another ADC can be input. This is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. Figure 14 shows an example with two daisy chained devices. The MSB of converter A will appear at SDO of converter B after 16 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK.
CONVERT OVDD CHAIN RDL/SDI CNV LTC2383-16 A SCK SDO OVDD CHAIN RDL/SDI CNV LTC2383-16 B SCK BUSY SDO IRQ DATA IN DIGITAL HOST
CLK
238316 F14a
CONVERT ACQUIRE CHAIN = OVDD RDL/SDIA = 0
POWER-DOWN ACQUIRE
POWER-UP
CONVERT
tCYC tCNVL
CNV
BUSY tBUSYLH
tCONV
tSCKCH
tSCKH 16 tHSDO tDSDO 17 18 tSCKL 30 31 32
SCK
1
2
3 tSSDISCK tHSDISCK
14
15
SDOA = RDL/SDIB
D15A tDSDOBUSYL
D14A
D13A
D1A
D0A
SDOB
D15B
D14B
D13B
D1B
D0B
D15A
D14A
D1A
D0A
238316 F14
Figure 14. Chain Mode Timing Diagram
238316f
18
LTC2383-16 BOARD LAYOUT
To obtain the best performance from the LTC2383-16 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1571A, the evaluation kit for the LTC2383-16.
Partial Top Silkscreen
238316 BL01
238316f
19
LTC2383-16 BOARD LAYOUT
Partial Layer 1 Component Side
238316 BL02
Partial Layer 2 Ground Plane
238316 BL03
238316f
20
LTC2383-16 BOARD LAYOUT
Partial Layer 3 PWR Plane
238316 BL04
Partial Layer 4 Bottom Layer
238316 BL05
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21
LTC2383-16
BOARD LAYOUT
1
2
3
C18 OPT -IN1 C39 OPT R1 NPO 100 OUT2 5 R36 49.9 LTC2383-16 GND GND GND GND IN- RDL/SDI R7 1k 3 6 10 16 1 C10 OPT R35 OPT R38 OPT C19 3300pF 1206 NPO R1 100 IN+ VDD 2 OVDD 15 7 8 REF REF1 CNV SCK SDO BUSY R45 O R1 O C61 10F 6.3V
R15 1k
R9 1k
C42 15pF
+2.5V R34 O R37 1k C62 10F V+ C57 0.1F V- C55 1F 6 C45 V - 10F
C8 1F
R18 1k
JP2 CM
Partial Schematic of Demoboard
1
VREF/2 EXT
2
3
E7 C43 1F C59 1F C44 1F C60 1F 9V TO 10V
HD1X3-100
EXT_CM
C46 1F
R40 1k
C63 10F 6.3V
COUPLING AC DC
JP5 HD1X3-100 SDO
1
2
AIN - C49 OPT
R39 O
3
R41 OPT
C47 OPT C48 10F 6.3V
+ -
2 +IN2
- +
22
R1 33 +3.3V C2 0.1F JP4 REF 1 +3.3V 6 CLR\ Q\ 3 3 5 DB17 DB16 J2 CON-EDGE 40-100 PR\ Q 5 U3 NL17SZ74 C56 0.1F JP6 FS 1 2 3 HD1X3-100 U6 OPT NC7SZ66P5X 5 CNV VCC 9 2B A1 13 SCK OE 4 14 SDO GND 11 BUSY 3 12 RD +3.3V +3.3V C13 0.8VREF 0.1F VREF R8 33 DC590 DETECT TO CPLD 4 R4 7 33 4 CP GND 8 D VCC U4 NC7SVU04P5X 2 CNVST_33 FROM CPLD 2 +3.3V C3 0.1F +3.3V C4 0.1F 5 4 2 C11 0.1F C12 1F HD1X3-100 R31 OPT V+ +3.3V U15 7 LT6350CMS8 SHDN C7 0.1F OUT1 4 C58 OPT C9 10F 6.3V C10 0.1F R32 49.9 +2.5V C6 10F 6.3V DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 4 5 3 U9 NC7SZ04P5X 2 R17 R13 2k 1k C15 0.1F CLKOUT C16 1 0.1F 3 V+ C20 47F 6.3V 0805 1 4 2 EXT 6652 9V TO 10V 3 E6 EXT_REF R3 CLK 33 TO CPLD U10 LTC6652AHMS8-2.5 8 1 DNC GND 2 7 VIN GND 3 6 VOUT SHDN 5 4 GND GND R32 O 8 +IN1 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J3 DC590 1 3 5 7 9 11 13 2 4 6 8 10 12 14 R10 4.99k 6 5 7 3 2 1 VSS 4 U7 C14 0.1F 8 24LC025-I/ST VCC SCL SCK SDA WP CNV ARRAY A2 EEPROM A1 A0 R11 4.99k R12 4.99k
+3.3V
C5 0.1F
+3.3V C1 0.1F R2 1k
5
CLKIN
2
R5 49.9 1206
U2 R6 3 U8 3 NC7SZ04P5X NC7SVU04P5X 1k
COUPLING AC DC
JP1 HD1X3-100
AIN+
R14 O
C17 10F
238316f
LTC2383-16 PACKAGE DESCRIPTION
DE Package 16-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1732 Rev O)
4.00 0.10 (2 SIDES) 0.70 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 0.25 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.200 REF R = 0.05 TYP 3.00 0.10 (2 SIDES) 3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER
(DE16) DFN 0806 REV O
R = 0.115 TYP 9
0.40 0.10 16
3.60 0.05 2.20 0.05
8 0.75 0.05
1 0.23 0.05 0.45 BSC
3.15 REF 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
MS Package 16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev O)
4.039 0.102 (.159 .004) (NOTE 3) 16151413121110 9
0.889 (.035
0.127 .005)
0.280 0.076 (.011 .003) REF
5.23 (.206) MIN
3.20 - 3.45 (.126 - .136)
GAUGE PLANE
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
0.305 0.038 (.0120 .0015) TYP
0.50 (.0197) BSC
0.18 (.007)
0.53 0.152 (.021 .006) DETAIL "A"
12345678 1.10 (.043) MAX
0.86 (.034) REF
RECOMMENDED SOLDER PAD LAYOUT
SEATING NOTE: PLANE 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 -0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.1016 (.004
0.0508 .002)
MSOP (MS16) 1107 REV O
238316f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2383-16 TYPICAL APPLICATION
ADC Driver: Single-Ended Input to Differential Output with Filter
0 -20 SINGLE-ENDED INPUT SIGNAL LPF1 500 8 6600pF 1 LT6350 4 LPF2 50 3300pF 50 100 BW = 482kHz IN-
238316 TA03
100
-40 AMPLITUDE (dBFS) IN+ LTC2383-16 -60 -80 -100 -120 -140
SNR = 92.2dB THD = -106.2dB SINAD = 92dB SFDR = 110.4dB
+ -
RINT
RINT
BW = 48kHz
2
+ -
VCM = VREF/2
5
+ -
-160 -180 0 100 200 300 FREQUENCY (kHz) 400 500
238316 TA04
RELATED PARTS
PART NUMBER ADCs LTC2393-16 LTC2392-16 LTC2391-16 LTC1864/LTC1864L LTC1865/LTC1865L LTC2302/LTC2306 DACs LTC2641 LTC2630 REFERENCES LTC6652 LTC6655 AMPLIFIERS LT6350 LT6200/LT6200-5/ LT6200-10 LT6202/LT6203 LTC1992 Low Noise Single-Ended-To-Differential ADC Driver Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time, DFN-8 or MSOP-8 Packages 165MHz/800MHz/1.6GHz Op Amp with Unity Gain/AV = 5/AV = 10 Single/Dual 100MHz Rail-to-Rail Input/Output Noise Low Power Amplifiers Low Power, Fully Differential Input/Output Amplifier/Driver Family Low Noise Voltage: 0.95nV/Hz (100kHz), Low Distortion: -80dB at 1MHz, TSOT23-6 Package 1.9nVHz, 3mA Maximum, 100MHz Gain Bandwidth 1mA Supply Current Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/C Max Tempco, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/C Max Tempco, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package 16-Bit Single Serial VOUT DACs 12-/10-/8-Bit Single VOUT DACs 1LSB INL, 1LSB DNL, MSOP-8 Package, 0V to 5V Output SC70 6-Pin Package, Internal Reference, 1LSB INL (12Bits) 16-Bit, 1Msps Parallel/Serial ADC 16-Bit, 500Ksps Parallel/Serial ADC 16-Bit, 250Ksps Parallel/Serial ADC 16-bit, 250ksps/150ksps 1-Channel Power ADC 16-bit, 250ksps/150ksps 2-Channel Power ADC 12-Bit, 500ksps, 1-/2-Channel, Low Noise, ADC 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP Package, Pin Compatible with the LTC2392-16, LTC2391-16 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP Package, Pin Compatible with the LTC2393-16, LTC2391-16 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP Package, Pin Compatible with the LTC2393-16, LTC2392-16 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package 5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-8 Package 5V Supply, 14mW at 500ksps, 10-Pin DFN Package 3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package DESCRIPTION COMMENTS
LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC
238316f
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0810 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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